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Article
Publication date: 30 August 2019

Mingwei Hu, Hongguang Wang, Xinan Pan and Yong Tian

The purpose of this paper is to search the optimal arrangement scheme of random motion accuracy of joints for optimal synthesis of pose repeatability which can make robot design…

Abstract

Purpose

The purpose of this paper is to search the optimal arrangement scheme of random motion accuracy of joints for optimal synthesis of pose repeatability which can make robot design more reasonable and reduce the development cost of robots.

Design/methodology/approach

In this paper, a mathematical model of pose repeatability, which includes positioning repeatability and orientation repeatability of robots, is established. According to the ISO 9283 standard, an optimal synthesis method of pose repeatability for collaborative robots is introduced, and three optimization objective functions are proposed. The optimization model is solved by using numerical analysis software, and the optimal arrangement scheme of random motion accuracy of joints is obtained which meets the requirements of pose repeatability of robot.

Findings

It is found that, in three optimization objective functions, the single-objective evaluation function of maximization of joint motion error is more suitable for optimal synthesis of pose repeatability. In practice, due to the safety factor, the test results of pose repeatability are better than the results of optimal synthesis of pose repeatability.

Practical implications

This method makes robot design more reasonable and reduces the development cost of robots.

Originality/value

This work is the first time to optimize the orientation repeatability of collaborative robots. Because the pose repeatability of most robots is tested by the ISO 9283 standard, so this method which is based on this standard is more suitable for the performance requirements of robot products.

Details

Industrial Robot: the international journal of robotics research and application, vol. 46 no. 6
Type: Research Article
ISSN: 0143-991X

Keywords

Article
Publication date: 3 August 2020

Chen Kuilin, Feng Xi, Fu Yingchun, Liu Liang, Feng Wennan, Jiang Minggang, Hu Yi and Tang Xiaoke

The data protection is always a vital problem in the network era. High-speed cryptographic chip is an important part to ensure data security in information interaction. This paper…

Abstract

Purpose

The data protection is always a vital problem in the network era. High-speed cryptographic chip is an important part to ensure data security in information interaction. This paper aims to provide a new peripheral component interconnect express (PCIe) encryption card solution with high performance, high integration and low cost.

Design/methodology/approach

This work proposes a System on Chip architecture scheme of high-speed cryptographic chip for PCIe encryption card. It integrated CPU, direct memory access, the national and international cipher algorithm (data encryption standard/3 data encryption standard, Rivest–Shamir–Adleman, HASH, SM1, SM2, SM3, SM4, SM7), PCIe and other communication interfaces with advanced extensible interface-advanced high-performance bus three-level bus architecture.

Findings

This paper presents a high-speed cryptographic chip that integrates several high-speed parallel processing algorithm units. The test results of post-silicon sample shows that the high-speed cryptographic chip can achieve Gbps-level speed. That means only one single chip can fully meet the requirements of cryptographic operation performance for most cryptographic applications.

Practical implications

The typical application in this work is PCIe encryption card. Besides server’s applications, it can also be applied in terminal products such as high-definition video encryption, security gateway, secure routing, cloud terminal devices and industrial real-time monitoring system, which require high performance on data encryption.

Social implications

It can be well applied on many other fields such as power, banking, insurance, transportation and e-commerce.

Originality/value

Compared with the current strategy of high-speed encryption card, which mostly uses hardware field-programmable gate arrays or several low-speed algorithm chips through parallel processing in one printed circuit board, this work has provided a new PCIe encryption card solution with high performance, high integration and low cost only in one chip.

Details

Circuit World, vol. 47 no. 2
Type: Research Article
ISSN: 0305-6120

Keywords

Article
Publication date: 8 June 2012

Baohua Yang, Shili Fang and Jinshuai Zhao

The purpose of this paper is to attempt to realize a complete analysis at scenario deduction of unconventional incidents coupling based on the GERTS network method.

Abstract

Purpose

The purpose of this paper is to attempt to realize a complete analysis at scenario deduction of unconventional incidents coupling based on the GERTS network method.

Design/methodology/approach

Starting from the manifestation of coupling objects, three types of emergency coupling are analyzed according to different rules, which are “events‐events” coupling, “event‐factors” coupling and “factors‐factors” coupling. Then the coupling mechanism for emergency is focused on analyzing, and the concepts of three types of coupling are put forward, at the same time, three quantitative models for coupling mechanisms are present. Also, a case was discussed to verify the analysis of coupling mechanism of emergency.

Findings

According to the types of factors rules, the classes of coupling of emergency have been divided into three types. The coupling mechanism of emergency can be used to describe the novel coupling models.

Practical implications

This research provides the method for coupling analysis in the scenario of unconventional incidents and guides the emergency managers to develop contingency strategies.

Originality/value

The paper succeeds in constructing a novel coupling model for emergency, and it could provide an effective tool for a quantitative study on unconventional incidents coupling.

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